楼主所在的组是Apple的SOC核心部门，现在扩招，至少有两个Junior ASIC Design
Engineer的open。楼主是TL，这两个open都是参与楼主负责的project。目前迫切需要
的是Junior 的 ASIC Designer (1-3 yrs experience) 的 candidate。希望你对ASIC
Design， RTL coding， scripting和一些architecture感兴趣，愿意学习和承担task
General JD as follows:
HRDWR
Key Qualifications
RTL Logic Design experience of multi-million gate ASICs
Hands-on experience in all aspects of the chip development process with
proficiency in front-end tools and methodologies
Experience writing specifications and converting them to design
Experience with multiple clock domains and asynchronous interfaces
Experience or knowledge of system architecture, CPU & IP Integration, and
power and clock management designs desirable.
Ability to communicate effectively across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl or Tcl a plus
Description
As an ASIC Design Engineer, your responsibilities span various aspects of
SOC design:
Write microarchitecture and/or design specifications
Design, implement and debug complex logic designs
Integrate complex IPs into the SOC
Support all front-end integration activities like Lint, CDC, Synthesis, and
ECO
Work with other engineers that are members of the SOC Design, SOC Design
Verification, Emulation, STA, and Physical Design teams
Collaborate with software and systems teams to ensure a high-quality end
product
简历请发至 titaniumsiegfried@gmail.com
也欢迎grads的简历，楼主会做筛选。如果有拿到电面，请务必提前联系楼主沟通面试
流程和注意事项