Location: San Jose, California
Responsibilities:
Work closely with the design team to review and understand specifications /
architectures / micro-architectures
Define test plans
Develop IP/block level and chip level verification environments
Produce functional / code coverage metrics
Run RTL/gate level simulations
Run regression and debug / triage failures in simulation environment
Work with validation/software teams to debug issues in the lab
Requirements:
BSEE with 5+ years or MSEE with 3+ years experience
Advanced knowledge of standard ASIC/FPGA verification flows including
simulation, testbench development, and post silicon validation
Excellent knowledge of System Verilog and Verilog
Experience in developing test benches using the OVM, VMM or UVM methodology
Good knowledge with C/C++
Experience with either Perl or Python scripts
Knowledge of industry high speed interface standard protocols (PCI Express,
DDR, NAND Flash etc.) strongly desired
Experience in computer storage and networking is desired
Should be a team player with excellent communication skills and the desire
to take on diverse challenges
站内或者email：jobopening666@gmail.com